1. Field of the Invention
The present invention relates to a semiconductor delay circuit and, particularly, to a semiconductor delay circuit having a function of regulating a delay time of an output signal to a desired value.
2. Description of Related Art
With the progression of the semiconductor technology, an operating speed of a semiconductor integrated circuit (LSI) is being increased. For example, a dynamic random access memory (DRAM) having an operation clock frequency of 200 MHz or more has been developed and it is expected that a DRAM having operation clock frequency of 400 MHz or more will be realized in the near future.
With increase of the operating speed of the semiconductor integrated circuit, a propagation delay of a signal on a printed circuit board becomes more and more important. For example, considering a system in which a logic LSI including such as a CPU and a plurality of DRAM's are mounted on a printed circuit board, distances between the logic LSI and the individual DRAMs are generally different. Therefore, the propagation delay times from the respective DRAM's to the logic LSI are different mutually. Therefore, there is a problem that the higher the operating speed of the DRAM makes the smaller the margin of an output timing due to the difference in propagation delay time. For example, there is a possibility of occurrence of an erroneous operation in a certain DRAM (for example, a DRAM which is farthest from a logic LSI) due to deviation of signal timing.
As one of solutions to this problem, it is considered to regulate delay times in a semiconductor integrated circuit. In the case mentioned above, for example, the deviation of timing may be corrected by regulating the delay times of the DRAMs to desired values, respectively.
A variety of techniques for regulating delay time have been proposed. For example, a semiconductor integrated circuit has been proposed in Japanese Patent Application Laid-open No. H2-139957, in which series-connected n delay circuits are connected to an input terminal and outputs derived from the respective delay circuits or outputs each derived for every plurality of delay circuits are supplied to a selector, and one of the outputs is selected thereby according to a control signal supplied from a control terminal to regulate the delay time which is output to an internal circuit.
An another example, in, for example, Japanese Patent Application Laid-open No. H8-274601 which discloses a circuit for regulating a delay time by supplying outputs of a plurality of series connected delay circuits to a selector and selecting one of them, a signal input to a delay regulation terminal is input to a flip-flop and synchronized with one of the outputs of the delay circuits whose delay time is the longest as a selection signal of the selector.
These prior art techniques have the following problems. That is, a first problem is that it is difficult to finely regulate the delay time. This is because it is impossible to make a difference between delay outputs smaller than a delay time corresponding to series-connected two inverters which constitute a delay circuit since a plurality of such delay circuits are connected in series.
A second problem is that it is impossible to sufficiently increase the number of regulating steps. The reason for this is that, since it is impossible to finely regulate the delay time in relation to the first problem, the longest delay time becomes too large when the number of regulating steps is increased.